Statistical Timing-Yield Optimization via Latch Substitution∗

The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern circuit designs may suffer from uncertain delays, not predictable in the design phase or even after manufacturing. This paper presents an optimization technique to make sequential circuits robust against delay variations and thus maximize timing yield. By trading larger flip-flops for smaller latches, the proposed approach can be used as a post-synthesis or post-layout optimization tool, allowing accurate timing information to be available. Experimental results show an average of 26% timing yield improvement, and suggest that our method is promising for high speed designs tolerating clock variations.